Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
نویسندگان
چکیده
منابع مشابه
Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical m...
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ژورنال
عنوان ژورنال: Journal of Electronic Testing
سال: 2012
ISSN: 0923-8174,1573-0727
DOI: 10.1007/s10836-012-5314-3